The present invention relates to a semiconductor device and a process for producing the same. More particularly, the present invention pertains to a semiconductor device having a memory comprising a capacitor and at least one transistor and also to a process for producing the same.
High integration of semiconductor devices, for example, dynamic random access memories (hereinafter abbreviated as "DRAMs"), has been realized at surprising speed. The mainstream of DRAMs which are presently produced are 256-kilobit DRAMs, but the production of 1-megabit DRAMs has already been initiated. The high integration of semiconductor devices has been achieved mainly by reduction in the size of memory cells. The memory cell area was reduced to about 40% of that required in the previous generation and with respect to each new generation of development, i.e., from 64-kilobit DRAMs to 256-kilobit DRAMs and further to 1-megabit DRAMs. The capacitor area has also been reduced substantially proportionally to the memory cell area. However, if the capacitor area is reduced with the thickness of the capacitor insulator being maintained at a constant level, the capacitance of the storage capacitor decreases, which leads to problems, for example, including a lowering in the signal-to-noise ratio and that pertaining data reversal (so-called soft-errors) due to alpha-particles, and thus resulting in considerably lowering in the reliability. For this reason, the thickness of the capacitor insulator has been reduced in order to prevent a lowering in the capacitance of the storage capacitor when the capacitor area is reduced. In the case of 1-megabit DRAMs, the film thickness of the capacitor insulator has already been reduced to 10 nm in terms of the silicon dioxide equivalent, and in the case of 4-megabit DRAMs, an insulating film having a thickness of from 4 to 6 nm is considered to be needed. The silicon dioxide equivalent thickness d is a film thickness which is calculated from the measured capacitance C assuming that the capacitor insulator is a silicon dioxide film formed by thermal oxidation. It may be expressed as follows: ##EQU1## where S is the capacitor area, and .epsilon. is dielectric constant of the silicon dioxide.
As the capacitor insulator becomes reduced in thickness, i.e., is thinned, as described above, a problem which arises is that a tunneling current flows between the electrodes of the capacitor which results in the disappearance or dissipation of the stored charge. This problem is discussed, for example, in Solid-State Electronics, vol. 10, pp. 865-873 (1967).
In order to solve the above-described problem, a capacitor having a stacked structure was proposed and discussed in Japanese Patent Publication No. 61-55258 (1986). In the stacked capacitor, a part of it is formed so as to be stacked over a MOS transistor and over an insulator for isolation, and it is therefore possible to utilize the region over these elements as a part of the capacitor and hence to increase the capacitor area in comparison with the conventional structure wherein the capacitor and the MOS transistor are formed on the same plane. Accordingly, even if an insulator having a thickness of 10 nm in terms of the silicon dioxide equivalent is employed, it is possible to ensure a capacitance needed in a 4-megabit DRAM, and thus it is possible to prevent disappearance of the stored charge.
However, if it is intended to further increase the integration density and to realize a 16-megabit DRAM, for example, it is necessary to employ an insulator having a thickness of about 5 nm in terms of the silicon dioxide equivalent, and the problem of the disappearance of the charge due to the tunneling current arises again. It has been reported that an insulator having a thickness of 5 nm is barely fit for practical application, however, it is extremely difficult to further reduce the film thickness. In addition, as the thickness of the insulator is extremely reduced, it is feared that the yield may be lowered by variations in the film thickness, and it is therefore difficult to further increase the integration density.
It is necessary that in order to increase the capacitance the distance between each pair of adjacent capacitors should be minimized. However, the highest resolution obtained by the existing optical lithography technology regarding such distance is on the order of 0.6 .mu.m and it is therefore necessary to adopt various complicated techniques in order to reduce the distance between each pair of adjacent capacitor storage electrodes. This problem also hinders achievement of high density and high integration.